With the increasing down-scaling of semiconductor devices, various processing techniques, such as, photolithography, and the like are adapted to allow for the manufacture of devices with increasingly smaller dimensions. However, as semiconductor processes require smaller process windows, the manufacture of these devices have approached and even surpassed the theoretical limits of photolithography equipment. As semiconductor devices continue to shrink, the spacing desired between elements (i.e., the pitch) of a device is less than the pitch that can be manufactured using traditional optical masks and photolithography equipment.
One approach used to achieve the higher resolutions to manufacture is to use multiple pattern lithography. In an example, dummy lines (e.g., at a minimum available pitch) are formed on underlying layers for patterning and sidewall spacers are formed on and around the dummy lines. Then, the dummy lines are removed and the sidewall spacers are left on the substrate. The sidewall spacers are used as patterning masks to transfer desired patterns to the underlying layers. In this manner, line spacing at approximately half the minimum pitch can be achieved.